Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.3.5. SCFIFO ALMOST_EMPTY Functional Timing

In SCFIFO, the almost_empty is asserted only when the usedw is less than the almost_empty_value that you set. The almost_empty signal does not consider the data readiness at the output. When the almost_empty_value is set too low, it is possible to observe that SCFIFO asserts the empty signal without asserting the almost_emtpy signal.

Figure 36. Example of empty Signal Assertion without Asserting almost_empty Signal

In this example, the almost_empty_value is 1 which means the almost_empty will assert when usedw is 0. There are three words in the FIFO before the read request is received. After the first read, the wrreq asserts and the rdreq signal remains high. The usedw remains at 2. In the next cycle, the wrreq de-asserts but there is another rdreq going on. The usedw decrease to 1 and the almost_emtpy signal remains low. However, the write data has not been written into the FIFO due to the write latency. The empty signal asserts to indicate the FIFO is empty.

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