Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.2. eSRAM Intel® Agilex™ FPGA IP

The basic building block of the eSRAM Intel® Agilex™ FPGA IP is a bank, which consists of an array of 1K x 64-bit SRAM blocks.

32 eSRAM banks combine to form a channel.

Figure 28. eSRAM Channel

Four memory ports combine to form an eSRAM system, with each port consists of two channels.

Figure 29. eSRAM System

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