Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.16. FIFO Intel® FPGA IP Parameters

Table 54.  FIFO Intel® FPGA IP Parameters DescriptionThis table lists the parameters for the FIFO Intel® FPGA IP core.
Parameter Legal Values Description
Parameter Settings: Width, Clk, Synchronization
How wide should the FIFO be? Specifies the width of the data and q ports.
How deep should the FIFO be? Note: You could enter arbritary values for width 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and 131072 Specifies the depth of the FIFO, which is always a power of 2.
Do you want a common clock for reading and writing the FIFO?
  • Yes, synchronize both reading and writing to 'clock'. Create one set of full/empty control signals.
  • No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock.
Parameter Settings: SCFIFO Options
Would you like to disable any circuitry protection?
  • full
  • empty
  • usedw[] (number of words in FIFO).

    Note: You can use the MSB to generate a half full flag.

  • almost full becomes true when usedw[] is greater than or equal to
  • almost empty becomes true when usedw[] is less than
  • Asyncronous clear
  • Syncronous clear (flush the FIFO)
On/Off
Parameter Settings: DCFIFO 1
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock., the following options are available:

Total latency, clock synchronization, metastability protection, area, and fmax options must be set as a group. Total latency is the sum of two write clock rising edges and the number of read clocks selected below.

Which option(s) is most important to the DCFIFO? (Read clk sync stages, metastability protection, area, fmax)

Which type of optimization do you want?

  • Minimal setting for unsynchronized clocks. 2 sync stages, good metastability, medium size, good fmax.
  • Best metastability protection, best fmax, unsynchronized clocks. 3 or more sync stages, best metastability protection, largest size, best fmax.
Specify total latency, clock synchronization, metastability protection, area, and fmax.
  • Minimal setting for unsynchronized clocks—This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.
  • Best metastability protection, best fmax, unsynchronized clocks—This option uses three or more synchronization stages with the best metastability protection. It uses the largest size but gives the best fMAX.
More options When you select Best metastability protection, best fmax, unsynchronized clock, the following option is available:
  • How many sync stages?
3, 4, 5, 6, 7, 8, and 9 Specifies the number syncronization stages.
Timing Constraint
  • Generate SDC file and disable embedded timing constraint
On/Off Generate a SDC file with correct timing constraints. Embedded set_false_path assignment is disabled. The new timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay. For more infomation on the timing constraint usage, refer to user guide.
Parameter Settings: DCFIFO 2
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock., the following options are available:

Which optional output control signals do you want?

usedw[] is the number of words in the FIFO.

On/Off
Read-side
  • full
  • empty
  • usedw[]

Note: These signals are syncronous to 'rdclk'.

Write-side
  • full
  • empty
  • usedw[]

Note: These signals are syncronous to 'wrclk'.

More options
  • Add an extra MSB to usedw port(s). Note: You can use the MSB to generate a half-full flag.
  • Asynchronous clear
  • Add circuit to synchronize 'aclr' input with 'wrclk'
  • Add circuit to synchronize 'aclr' input with 'rdclk'
On/Off
Parameter Settings: Rdreq Option, Blk Type
Which kind of read access do you want with the 'rdreq' signal?
  • Normal FIFO mode.
  • Show-ahead synchronous FIFO mode.
Specifies whether the FIFO is in Legacy mode or in Show-ahead mode.
  • Normal FIFO mode—The data becomes available after 'rdreq is asserted. 'rdreq' acts as a read request.
  • Show-ahead synchronous FIFO mode—The data becomes available before 'rdreq' is asserted. 'rdreq' acts as a read acknowledge. Note: This mode suffers a performance penalty.
What should the memory block type be?
  • Auto
  • MLAB
  • M20K
  • M144K
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to: Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and 131072 Specifies the maximum block depth in words.
Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9. On/Off
Parameter Settings: Optimization, Circuitry Protection
Would you like to register the output to maximize performance but use more area?
  • Yes (best speed)
  • No (smallest area)
Specifies whether to register the RAM output.
Implement FIFO storage with logic cells only, even if the device contains memory blocks. On/Off Specifies whether to implement FIFO storage with logic cells only.
Would you like to disable any circuitry protection (overflow checking and underflow checking)?
If not required, overflow and underflow checking can be disabled to improve performance.
  • Disable overflow checking. Writing to a full FIFO will corrupt contents.
  • Disable underflow checking. Reading from an empty FIFO will corrupt contents
On/Off Specifies whether to disable any circuitry protection for overflow
Would you like to enable ECC?
  • Enable error checking and correcting (ECC)
On/Off Specifies whether to enable error checking and correcting feature.

Did you find the information on this page useful?

Characters remaining:

Feedback Message