Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters

This table lists the parameters for the ROM: 2-PORT Intel® FPGA IP.
Table 27.  ROM: 2-PORT Intel® FPGA IP Parameter Settings
Parameter Legal Values Description
Parameter Settings: Widths/Blk Type
How do you want to specify the memory size?
  • As a number of words
  • As a number of bits
Determines whether to specify the memory size in words or bits.
How many words of memory? 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, or 65536 Specifies the number of words.
Use different data widths on different ports On/Off Specifies whether to use different data widths on different ports.
How wide should the ‘q_a’ output bus be? Specifies the width of the ‘q_a’ and ‘q_b’ output ports.
How wide should the ‘q_b’ output bus be?
RAM block type Auto, M20K Specifies the memory block type. The types of memory block that are available for selection depends on your target device
Set the maximum block depth to:
  • Auto: Auto, 512, 1024, or 2048
  • M20K: Auto, 512, 1024, or 2048
Specifies the maximum block depth in words. This option is enabled only when you choose Auto as the memory block type.
Parameter Settings: Clks/Rd
What clocking method would you like to use?
  • Single
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Customize clocks for A and B ports

Specifies the clocking method to use.

  • Single—A single clock and a clock enable controls all registers of the memory block
  • Dual clock: use separate ‘input’ and ‘output’ clocks—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode.
  • Customize clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
Create a ‘rden_a’ and ‘rden_b’ read enable signals On/Off Specifies whether to create read enable signals.
Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered?

Read output ports

On/Off Specifies whether to register the read output ports.
More Options Registered Q Output Ports
  • ‘q_a’ port
  • ‘q_b’ port
On/Off Turn on if you want the registered ‘q_a’ and ‘q_b’ ports to be affected by the asynchronous clear signal.
  • q_a port—Specifies whether to register the ‘q_b’ output port.
  • q_b port—Specifies whether to register the ‘q_b’ output port.
Use clock enable for port A input registers On/Off Specifies whether to use clock enable for port A input registers.
Use clock enable for port A output registers On/Off Specifies whether to use clock enable for port A output registers.
Use clock enable for port B input registers On/Off Specifies whether to use clock enable for port B input registers.
Use clock enable for port B output registers On/Off Specifies whether to use clock enable for port B output registers.
Aclr Options
  • ‘q_a’ port
  • ‘q_b’ port
On/Off Specifies whether the registered ports should be cleared by the asynchronous clear port.
Sclr Options
  • ‘q_a’ port
  • ‘q_b’ port
On/Off Specifies whether the registered ports should be cleared by the synchronous clear port.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

In ROM mode, you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default.
The initial content file should conform to which port’s dimensions?
  • PORT_A
  • PORT_B
Specifies whether the initial content file conforms to port A or port B.
Parameter Settings: Performance Optimization
Enable Force-to-Zero On/Off Specifies whether to set the output to zero when you deassert the read enable signal.

Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block.

Which timing/power optimization option do you want to use?
  • Auto
  • High Speed
  • Low Power
Specifies the timing/power optimization option to use. This option is only applicable when you select M20K memory type on Intel® Agilex™ devices.

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