Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings

Table 56.  Shift Register (RAM-based) Intel® FPGA IP Parameter SettingsThis table lists the parameter for the Shift Register (RAM-based) Intel® FPGA IP.
Configuration Setting Description
How wide should the "shiftin" input and the "shiftout" output buses be? Specify the width of the data input and output buses. This value is represented by the term w in the Shift Register Memory Configuration.
How many taps would you like? Specify the number of taps. This value is represented by the term n in the Shift Register Memory Configuration.
Create groups for each tap output Turn on this option to create separate groups for output data tapped from the register chain. 39
How wide should the distance between taps be? Specify the distance between taps. This value is represented by the term m in the Shift Register Memory Configuration. 40
Create a clock enable port Turn on this option to create an enable signal for register ports. The register ports are always enabled if this option is not turned on. 41
Create an asynchronous clear port Turn on this option to create an asynchronous clear signal. When asserted, the outputs of the shift register are immediately cleared.
Create a synchronous clear port Turn on this option to create a synchronous clear signal. When asserted, the outputs of the shift register are cleared at the next positive clock edge.
What should the RAM block type be? Choose the type of memory block that supports the feature, memory configuration, and capacity for your application. 42
Note:
  1. The widths of the shiftin input bus and shiftout output bus are identical, and they are not registered. However, the output data can be considered synchronous with the clock because the internal read address to the memory block is synchronous to the clock.
  2. The width of the output taps is the multiplication of w (width of input data) and n (number of taps). Also, the word from the MSB of the output taps is equivalent to the shiftout output bus.
39 The combination of these groups represent the taps[wn-1:0] bus.
40 The distance between taps, m, must be at least 3.
41 The registered port is referred to as the internal register at the memory address ports. The shiftin and shiftout ports are not registered.
42 For information about the chosen memory block type, refer to the TriMatrix Embedded Memory Block chapter of your target device handbook. You can also choose AUTO if you are not particular about the RAM block type used. With the AUTO option, the memory block type is determined by the Intel® Quartus® Prime software synthesizer or Fitter at compile time. To determine the type of memory block used, check the Intel® Quartus® Prime Fitter Report.

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