Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters

This table lists the parameters for the RAM: 4-PORT Intel® FPGA IP.
Table 25.  RAM: 4-PORT Intel® FPGA IP Parameter Settings
Parameter Legal Values Description
Parameter Settings: Widths/ Blk Type
How many words of memory? Specifies the number of bit words.
How wide should the ‘q_a’ and ‘q_b’ output bus be? Specifies the width of the input and output ports.
RAM block type
  • Auto
  • M20K
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to
  • Auto: Auto, 512, 1024, or 2048
  • M20K: Auto, 512, 1024, or 2048
Specifies the maximum block depth in words.
Parameter Settings: Clks/Rd, Byte En
Which clocking method do you want to use? Single Specifies the clocking method to use.

Single—A single clock and a clock enable controls all registers of the memory block.

Create ‘rden_a’ and ‘rden_b’ read enable signals

Specifies whether to create a read enable signal for ports A and B.
Byte Enable Ports
  • Create byte enable for port A
  • Create byte enable for port B
On/Off Specifies whether to create a byte enable for ports A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written.

What is the width of a byte for byte enables?

M20K: 5, 8, 9, or 10

Specifies the byte width of the byte enable port. The width of the data input port must be divisible by the byte size.

Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered?
Input registers:
  • All write input ports
  • raddress port
Output registers:
  • q_a port
  • q_b port
On/Off Specifies whether to register the read or write input and output ports.
Use clock enable for input and output registers. On/Off Specifies whether to turn on the option to create one clock enable signal for the input and output registers.
Create an ‘aclr’ asynchronous clear for the input ports or output ports.
Read Input Aclrs:
  • ‘rdaddress‘ for port A
  • ‘rdaddress‘ for port B
Output Aclrs:
  • q_a port
  • q_b port
On/Off Specifies whether to create an asynchronous clear port for the input ports or output ports.
Read input ports:
  • ‘rdaddress‘ for port A—Specifies whether the rdaddress for port A is cleared by the aclr port.
  • ‘rdaddress‘ for port B—Specifies whether the rdaddress for port B is cleared by the aclr port.
Output Aclrs:
  • q_a port—Specifies whether the q_a port is cleared by the aclr port.
  • q_b port—Specifies whether the q_b port is cleared by the aclr port.
Create an ‘sclr’ synchronous clear for the output ports.
Output Sclrs:
  • q_a port
  • q_b port
On/Off Specifies whether to create a synchronous clear port for the output ports.
Output Sclrs:
  • q_a port—Specifies whether the q_a port is cleared by the sclr port.
  • q_b port—Specifies whether the q_b port is cleared by the sclr port.
Parameter Settings: Output 1
How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port?

The output of port A will be ‘NEW’ while the output of port B will be ‘OLD’

Specifies the output behavior when read-during-write occurs.

Parameter Settings: Output 2
What should the ‘q_a’ output be when reading from a memory location being written to? Don't Care

Specifies the output behavior when read-during-write occurs.

What should the ‘q_b’ output be when reading from a memory location being written to?
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?

Type:

  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

To initialize the memory to zero, select No, leave it blank.

To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data.

Initialize memory content data to XX..X on power-up simulation On/Off
The initial content file should conform to which port's dimensions?
  • PORT_A
  • PORT_B
If you select to use the initial content file for memory content data, select the port the file should conform to.
Implement clock-enable circuitry for use in a partial reconfiguration region On/Off

Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.

Parameter Settings: Performance Optimization
Enable Force-to-Zero On/Off Specifies whether to set the output to zero when you deassert the read enable signal.

Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block.

Which timing/power optimization option do you want to use?
  • Auto
  • High Speed
  • Low Power
Specifies the timing/power optimization option to use. This option is only applicable when you select M20K memory type on Intel® Agilex™ devices.

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