Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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2.7. Force-to-Zero

The Force-to-Zero feature helps improve timing when a RAM memory block selected is larger than a single memory block. This feature is applicable only for M20K blocks.

For example, if the selected RAM memory block has a memory depth of 4096, the M20K block, which supports only a maximum memory depth of 2048, will require two RAMs to be multiplexed together. When you engage with this feature, you can replace OR gate with multiplexing circuitry at the output of the M20K block when performing address width stitching. As the MSB of address controls the read enable signal in the Force-to-Zero mode, the outputs of other memory blocks are forced to zero when the read enable signal is deasserted. This results the data output being read out from the output of the selected memory block only.

You have the option to turn on Enable Force-to-Zero feature in the parameter editors of the RAM/ROM IPs.

Note: When you turn on Enable Force-to-Zero feature, the read enable signal does not retain previous values when you deassert the signal.

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