Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.3.7. FIFO Metastability Protection and Related Options

The FIFO Intel® FPGA IP parameter editor provides the total latency, clock synchronization, metastability protection, area, and fMAX options as a group setting for the DCFIFO.
Table 44.  DCFIFO Group Setting for Latency and Related Options This table shows the available group setting.
Group Setting Comment
Lowest latency but requires synchronized clocks This option uses one synchronization stage with no metastability protection. It uses the smallest size and provides good fMAX.

Select this option if the read and write clocks are related clocks.

Minimal setting for unsynchronized clocks This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.
Best metastability protection, best fmax and unsynchronized clocks This option uses three or more synchronization stages with the best metastability protection. It uses the largest size but gives the best fMAX.

The group setting for latency and related options is available through the FIFO Intel® FPGA IP parameter editor. The setting mainly determines the number of synchronization stages, depending on the group setting you select. You can also set the number of synchronization stages you desire through the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters, but you must understand how the actual number of synchronization stages relates to the parameter values set in different target devices.

The number of synchronization stages set is related to the value of the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE pipeline parameters. For some cases, these pipeline parameters are internally scaled down by two to reflect the actual synchronization stage.

The following equation shows the relationship between the actual synchronization stage and the pipeline parameters:

Actual synchronization stage = value of pipeline parameter - 2

Note: The values assigned to WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters are internally reduced by 2 to represent the actual synchronization stage implemented. Thus, the default value 3 for these parameters corresponds to a single synchronization pipe stage; a value of 4 results in 2 synchronization stages, and so on. Choose 4 (2 synchronization stages) for metastability protection.

The Timing Analyzer includes the capability to estimate the robustness of asynchronous transfers in your design, and to generate a report that details the mean time between failures (MTBF) for all detected synchronization register chains. This report includes the MTBF analysis on the synchronization pipeline you applied between the asynchronous clock domains in your DCFIFO. You can then decide the number of synchronization stages to use in order to meet the range of the MTBF specification you require.

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