Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4. Intel® Agilex™ Embedded Memory IP References

You can access the features of the Intel® Agilex™ embedded memory using the on chip memory IPs in the Intel® Quartus® Prime software.
The On chip memory IPs include:
  • RAM: 1-Port Intel® FPGA IP—instantiates the single-port RAM
  • RAM: 2-Port Intel® FPGA IP—instantiates the dual-port and bidirectional-port RAM
  • RAM: 4-Port Intel® FPGA IP—instantiates the quad-port RAM
  • ROM: 1-Port Intel® FPGA IP—instantiates the single-port ROM
  • ROM: 2-Port Intel® FPGA IP—instantiates the dual-port and bidirectional-port ROM
  • eSRAM (Embedded Synchronous Random Access Memory) Intel® FPGA IP—instantiates the native eSRAM block
  • FIFO (First-In-First-Out) Intel® FPGA IP—instantiates the FIFO Intel® FPGA IP
  • Shift Register (RAM-based) Intel® FPGA IP—instantiates the Shift Register (RAM-based) Intel® FPGA IP

You can also infer memory functions from HDL code. The Intel® Quartus® Prime synthesis recognizes certain HDL code structures and automatically infers the appropriate IP or map directly to the device atoms. Refer to Inferring Memory Functions from HDL Code in the Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations for more information.

However, if you want to use some of the advanced memory features in the Intel FPGA devices, consider using the IP directly so that you can customize the ports and parameters easily.

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