Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
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4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect

The FIFO Intel® FPGA IP core supports the synchronous clear (sclr) and asynchronous clear (aclr) signals, depending on the FIFO modes.
The effects of these signals are varied for different FIFO configurations. The SCFIFO supports both synchronous and asynchronous clear signals while the DCFIFO support asynchronous clear signal and asynchronous clear signal that synchronized with the write and read clocks.
Note: For Intel® Agilex™ devices, you must assert either aclr or sclr upon power-up to guarantee correct functionality.
Table 45.   Synchronous Clear and Asynchronous Clear in the SCFIFO
Mode Synchronous Clear (sclr) 26 Asynchronous Clear (aclr)
Effects on status ports Deasserts the full and almost_full signals.
Asserts the empty and almost_empty signals.
Resets the usedw flag.
Commencement of effects upon assertion At the rising edge of the clock. Immediate (except for the q output)
Effects on the q output for normal output modes The read pointer is reset and points to the first data location. If the q output is not registered, the output shows the first data word of the SCFIFO; otherwise, the q output remains at its previous value. The q output remains at its previous value.
Effects on the q output for show-ahead output modes The read pointer is reset and points to the first data location. If the q output is not registered, the output remains at its previous value for only one clock cycle and shows the first data word of the SCFIFO at the next rising clock edge. 27

Otherwise, the q output remains at its previous value.

If the q output is not registered, the output shows the first data word of the SCFIFO starting at the first rising clock edge.

Otherwise, the q output remains its previous value.

Table 46.  Asynchronous Clear in DCFIFO
Mode Asynchronous Clear (aclr) aclr (synchronize with write clock) 28 29 aclr (synchronize with read clock) 30 31
Effects on status ports Deasserts the wrfull signal. The wrfull signal is asserted while the write domain is clearing which nominally takes three cycles of the write clock after the asynchronous release of the aclr input. The rdempty signal is asserted while the read domain is clearing which nominally takes three cycles of the read clock after the asynchronous release of the aclr input.
Deasserts the rdfull signal.
Asserts the wrempty and rdempty signals.
Resets the wrusedw and rdusedw flags.
Commencement of effects upon assertion Immediate.
Effects on the q output for normal output modes 32 The output remains unchanged if it is not registered. If the port is registered, it is cleared.
Effects on the q output for show-ahead output modes The output shows 'X' if it is not registered. If the port is registered, it is cleared.
26 The read and write pointers reset to zero upon assertion of either the sclr or aclr signal.
27 The first data word shown after the reset is not a valid Show-ahead data. It reflects the data where the read pointer is pointing to because the q output is not registered. To obtain a valid Show-ahead data, perform a valid write after the reset.
28 The wrreq signal must be low when the DCFIFO comes out of reset (the instant when the aclr signal is deasserted) at the rising edge of the write clock to avoid a race condition between write and reset. If this condition cannot be guaranteed in your design, the aclr signal needs to be synchronized with the write clock. This can be done by setting the Add circuit to synchronize 'aclr' input with 'wrclk' option from the FIFO parameter editor, or setting the WRITE_ACLR_SYNCH parameter to ON.
29 Even though the aclr signal is synchronized with the write clock, asserting the aclr signal still affects all the status flags asynchronously.
30 The rdreq signal must be low when the DCFIFO comes out of reset (the instant when the aclr signal is deasserted) at the rising edge of the read clock to avoid a race condition between read and reset. If this condition cannot be guaranteed in your design, the aclr signal needs to be synchronized with the read clock. This can be done by setting the Add circuit to synchronize 'aclr' input with 'rdclk' option from the FIFO parameter editor, or setting the READ_ACLR_SYNCH parameter to ON.
31 Even though the aclr signal is synchronized with the read clock, asserting the aclr signal affects all the status flags asynchronously.
32 For Intel® Agilex™ series, the DCFIFO only supports registered q output in Normal mode, and unregistered q output in Show-ahead mode.

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