Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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1.1. Intel® Agilex™ Embedded Memory Features

The Intel® Agilex™ devices contain three types of memory blocks: Embedded SRAM (eSRAM) blocks, M20K blocks, and memory logic array blocks (MLABs).
  • 18.432-Megabit (Mb) eSRAM blocks
    • High bandwidth and very high random transaction rate (RTR) on-chip memory block.
    • Each block consists of 8 channels and each channel has 32 banks.
    • Each bank is configurable to 1K depth and 64-bit data width.
    • Supports only simple dual-port RAM with concurrent read and write access per channel.
  • 20-kilobit (Kb) M20K blocks
    • Blocks of dedicated memory resources.
    • Ideal for larger memory arrays, while providing a large number of independent ports.
  • 640-bit MLABs
    • Memory blocks configured from enhanced dual-purpose logic array blocks (LABs).
    • Ideal for wide and shallow memory arrays.
    • Optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines.
    • Each MLAB is made up of ten adaptive logic modules (ALMs).

In Intel® Agilex™ devices, you can configure each ALM in the MLAB as ten 32×2 blocks. The Intel® Agilex™ devices provide one 32×20 simple dual-port SRAM block per MLAB.

The Intel® Agilex™ embedded memory blocks support the following operation modes:
  • Single-port
  • Simple dual-port
  • True dual-port
  • Simple quad-port
  • ROM
Note: Simple Quad-port mode is supported for the -E1V, -E2V and -E3V speed grades of the Intel Stratix 10 devices only.
Table 1.   Intel® Agilex™ Embedded Memory FeaturesThis table summarizes the features supported by the Intel® Agilex™ embedded memory blocks.
Features eSRAM M20K MLAB
Maximum operating frequency 750 MHz
  • 1 GHz (simple dual-port RAM mode)
  • 600 MHz (true dual-port and simple quad-port RAM mode)
1 GHz
Total RAM bits (including parity bits) 18.432 Mb 20,480 bits 640 bits
Byte enable N/A Supported Supported
Address clock enable

(address stall)

N/A Supported (only in simple dual-port RAM mode) Supported
Simple dual-port mixed width N/A Supported N/A
FIFO buffer mixed width N/A Supported N/A
Memory Initialization File (.mif) N/A Supported Supported
Dual-clock mode N/A Supported (only in simple dual-port RAM mode) Supported
Full synchronous memory Supported Supported Supported
Asynchronous memory N/A N/A Only for flow-through read memory operations
Power-up state N/A Output ports are cleared
  • Registered output ports are cleared
  • Unregistered output ports read memory contents
Asynchronous/Synchronous Clears N/A
  • Output registers and output latches
  • Supports asynchronous clear on read address registers (only in simple dual-port and simple quad-port modes)
Output registers and output latches
Write/read operation triggering Rising clock edges Rising clock edges Rising clock edges
Same-port read-during-write N/A Output ports set to New Data , Old Data, or Don't Care Output ports set to Don't Care
Mixed-port read-during-write Write-forwarding feature
  • ON = New Data
  • OFF = Don't Care
  • Simple Dual Port RAM: Output ports set to Old Data or Don't Care
  • True Dual Port RAM: Output ports set to Don't Care
  • Simple Quad Port: Output ports set to new_a_old_b
Output ports set to New Data, Old Data, or Don't Care
Error Correction Code (ECC) support
  • Built-in support ×64-wide simple dual-port mode
  • Built-in support ×32-wide simple dual-port mode
  • Parity bits

N/A

Force-to-Zero N/A Supported N/A
Coherent read memory N/A Supported N/A
Freeze logic N/A Supported N/A
True dual port (TDP) dual clock emulator N/A Supported N/A

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