1.1. Intel® Agilex™ Embedded Memory Features
- 18.432-Megabit (Mb) eSRAM blocks
- High bandwidth and very high random transaction rate (RTR) on-chip memory block.
- Each block consists of 8 channels and each channel has 32 banks.
- Each bank is configurable to 1K depth and 64-bit data width.
- Supports only simple dual-port RAM with concurrent read and write access per channel.
- 20-kilobit (Kb) M20K blocks
- Blocks of dedicated memory resources.
- Ideal for larger memory arrays, while providing a large number of independent ports.
- 640-bit MLABs
- Memory blocks configured from enhanced dual-purpose logic array blocks (LABs).
- Ideal for wide and shallow memory arrays.
- Optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines.
- Each MLAB is made up of ten adaptive logic modules (ALMs).
In Intel® Agilex™ devices, you can configure each ALM in the MLAB as ten 32×2 blocks. The Intel® Agilex™ devices provide one 32×20 simple dual-port SRAM block per MLAB.
- Simple dual-port
- True dual-port
- Simple quad-port
|Maximum operating frequency||750 MHz||
|Total RAM bits (including parity bits)||18.432 Mb||20,480 bits||640 bits|
|Address clock enable
|N/A||Supported (only in simple dual-port RAM mode)||Supported|
|Simple dual-port mixed width||N/A||Supported||N/A|
|FIFO buffer mixed width||N/A||Supported||N/A|
|Memory Initialization File (.mif)||N/A||Supported||Supported|
|Dual-clock mode||N/A||Supported (only in simple dual-port RAM mode)||Supported|
|Full synchronous memory||Supported||Supported||Supported|
|Asynchronous memory||N/A||N/A||Only for flow-through read memory operations|
|Power-up state||N/A||Output ports are cleared||
||Output registers and output latches|
|Write/read operation triggering||Rising clock edges||Rising clock edges||Rising clock edges|
|Same-port read-during-write||N/A||Output ports set to New Data , Old Data, or Don't Care||Output ports set to Don't Care|
|Mixed-port read-during-write||Write-forwarding feature
||Output ports set to New Data, Old Data, or Don't Care|
|Error Correction Code (ECC) support||
|Coherent read memory||N/A||Supported||N/A|
|True dual port (TDP) dual clock emulator||N/A||Supported||N/A|
Did you find the information on this page useful?