Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.3.4. FIFO Functional Timing Requirements

The wrreq signal is ignored (when FIFO is full) if you enable the overflow protection circuitry in the FIFO Intel® FPGA IP parameter editor, or set the OVERFLOW_CHECKING parameter to ON. The rdreq signal is ignored (when FIFO is empty) if you enable the underflow protection circuitry in the FIFO Intel® FPGA IP core interface, or set the UNDERFLOW_CHECKING parameter to ON.

If the protection circuitry is not enabled, you must meet the following functional timing requirements:

Table 40.  Functional Timing Requirements
DCFIFO SCFIFO
Deassert the wrreq signal in the same clock cycle when the wrfull signal is asserted. Deassert the wrreq signal in the same clock cycle when the full signal is asserted.
Deassert the rdreq signal in the same clock cycle when the rdempty signal is asserted. You must observe these requirements regardless of expected behavior based on wrclk and rdclk frequencies. Deassert the rdreq signal in the same clock cycle when the empty signal is asserted.
Figure 34. Functional Timing for the wrreq Signal and the wrfull SignalThis figure shows the behavior for the wrreq and the wrfull signals.
Figure 35. Functional Timing for the rdreq Signal and the rdempty SignalThis shows the behavior for the rdreq the rdempty signals.

The required functional timing for the DCFIFO as described previously is also applied to the SCFIFO. The difference between the two modes is that for the SCFIFO, the wrreq signal must meet the functional timing requirement based on the full signal and the rdreq signal must meet the functional timing requirement based on the empty signal.

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