Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters

This table lists the parameters for the ROM: 1-PORT Intel® FPGA IP.
Table 26.  ROM: 1-PORT Intel® FPGA IP Parameter Settings
Parameter Legal Values Description
Parameter Settings: General Page
How wide should the ‘q’ output bus be? Specifies the width of the ‘q’ output bus.
How many words of memory? Specifies the number of words.
What should the memory block type be? Auto, MLAB, M20K Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to
  • MLAB: Auto, 32
  • M20K: Auto, 512, 1024, 2048
Specifies the maximum block depth in words.
Which clocking method would you like to use?
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks

Specifies the clocking method to use.

  • Single clock—A single clock and a clock enable controls all registers of the memory block
  • Dual clock: use separate ‘input’ and ‘output’ clocks—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode.
Parameter Settings: Regs/Clken/Aclrs
Which ports should be registered?
The following options are available:
  • ‘address’ input port
  • ‘q’ output port
On/Off Specifies whether to register the input and output ports.
Use clock enable for port A input registers On/Off Specifies whether to use clock enable for port A input registers.
Use clock enable for port A output registers On/Off Specifies whether to use clock enable for port A output registers.
Create an ‘addressstall_a’ input port On/Off Specifies whether to create an addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers.
Create an ‘aclr’ asynchronous clear for the registered ports.

The following options are available:

  • ‘address’ port
  • ‘q’ port
On/Off Specifies whether the registered ports be affected by an asynchronous clear port.
Create a ‘sclr’ asynchronous clear for the registered ports.
  • ‘q’ port
On/Off Specifies whether the q port be affected by a synchronous clear port.
Create an ‘rden’ read enable signal On/Off Specifies whether to create a read enable signal.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

In ROM mode, you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default.
Parameter Settings: Performance Optimization
Enable Force-to-Zero On/Off Specifies whether to set the output to zero when you deassert the read enable signal.

Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block.

Which timing/power optimization option do you want to use?
  • Auto
  • High Speed
  • Low Power
Specifies the timing/power optimization option to use. This option is only applicable when you select M20K memory type on Intel® Agilex™ devices.

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