Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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2.2. Address Clock Enable Support

Intel® Agilex™ embedded memory blocks support address clock enable. When you enable address clock enable (addressstall = 1), it holds the previous address value.
Note:
  1. Only simple dual-port mode supports this feature.
  2. The addressstall signal cannot be asserted during the first clock cycle as this can result the output having non-deterministic values.

When you configure the memory blocks in dual-port mode, each port has its own independent address clock enable.

Figure 2. Address Clock EnableThis figure shows an address clock enable block diagram.


Figure 3. Address Clock Enable During Read CycleThis figure shows the address clock enable behavior during read cycle.


Figure 4. Address Clock Enable During Write CycleThis figure shows the address clock enable behavior during write cycle.


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