Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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Document Table of Contents

2.4.1. Parity Bit

The following describes the parity bit support for M20K blocks:
  • 8 parity bits are generated through the ECC encoder based on 32-bit input data width, resulting in up to a total of 40 bits of data width.
  • You can inject and flip the parity bits by using the ECC parity flip feature.

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