Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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2.13. Intel® Agilex™ Supported Embedded Memory IPs

Table 12.   Intel® Agilex™ Memory IPsThis table lists and describes the IPs that are supported in the Intel® Agilex™ embedded memory blocks.
IP Supported Memory Mode M20K Support MLAB Support eSRAM Support Description
RAM: 1-PORT Intel® FPGA IP Single-port RAM Yes Yes No You can perform only one read or one write operation at a time.

Use the read enable port to control the RAM output ports behavior during a write operation:

  • To retain the previous values that are held during the most recent active read enable—create a read-enable port and perform the write operation with the read enable port deasserted.
  • To show the new data being written, the old data at that address, or a Don't Care value when read-during-write occurs at the same address location—do not create a read-enable signal, or activate the read enable during a write operation.
RAM: 2-PORT Intel® FPGA IP Simple dual-port RAM Yes Yes No You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.
RAM: 2-PORT Intel® FPGA IP True dual-port RAM Yes No No You can perform any combination of two port operations: two reads, two writes, or one read and one write at single clocking mode.
RAM: 4-PORT Intel® FPGA IP Simple quad-port RAM Yes No No You can simultaneously perform two read and two write operations to different locations where the write addresses are specified at address_a and address_b signal/port, and the read addresses are specified at address2_a and address2_b signal/port.
ROM: 1-PORT Intel® FPGA IP Single-port ROM Yes Yes No

Only one address port is available for read operation.

You can use the memory blocks as ROM.

  • Initialize the ROM contents of the memory blocks using a .mif or .hex.
  • The address lines of the ROM are registered on M20K blocks but can be unregistered on MLABs.
  • The outputs can be registered or unregistered.
  • The output registers can be asynchronously or synchronously cleared.
  • The ROM read operation is identical to the read operation in the single-port RAM configuration.
ROM: 2 PORT Intel® FPGA IP Dual-port ROM Yes No No

The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation.

You can use the memory blocks as a ROM.

  • Initialize the ROM contents of the memory blocks using a .mif or .hex.
  • The address lines of the ROM are registered on M20K blocks.
  • The outputs can be registered or unregistered.
  • The output registers can be asynchronously or synchronously cleared.
  • The ROM read operation is identical to the read operation in the true dual-port RAM configuration.
Shift Register (RAM-based) Intel® FPGA IP Yes Yes No

Use the memory blocks as a shift register block to save logic cells and routing resources.

This mode is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross- correlation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers.

The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). You can cascade memory blocks to implement larger shift registers.

FIFO Intel® FPGA IP Yes Yes No

You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO functions to implement single- and dual-clock asynchronous FIFO buffers in your design.

For designs with many small and shallow FIFO buffers, the MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode.

eSRAM Intel® FPGA IP No No Yes

Use eSRAM memory (large memory) to perform a single read and write method. The eSRAM memory has 4 ports. Each port has dedicated write address and read address, along with write enable and read enable control signal to dynamically control the read and write operation.

CAUTION:
To avoid corrupting the memory contents, do not violate the setup time or hold time on any of the embedded memory block input registers during read and write operations. This limitation is applicable if you use the memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, simple quad-port RAM, or ROM mode.

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