Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.2.2.1. eSRAM Specifications

The following table summarizes the specifications of the eSRAM Intel® Agilex™ FPGA IP.
Table 31.  eSRAM Specifications
Feature Detail Value Description
Clock Frequency

-1

-2

-3

200 MHz - 750 MHz

200 MHz - 640 MHz

200 MHz - 500 MHz

Bank Capacity

64 Kb

Each bank is (1024) 1K x 64 bits

Banks per Channel

32

Channel Capacity

2.048 Mb

Ports per eSRAM

4

Each port consists of 2 channels.

eSRAM Capacity

16.384 Mb

Interface Data Width

x64

Maximum width
Read Latency 6

7 +2 7

Write Latency 0 + 2 7 There is a zero cycle latency for write commands issued to the eSRAM.
Power (per eSRAM system)

Static: 192 mW

Dynamic: 1.08 mW/MHz

6 Read latency is measured from a read command being presented to the interface to valid read data being returned.
7 +2 on read/write latency is added due to registers interfacing with eSRAM required to meet routing and timing requirement.

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