L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

1.2. Features

The Intel L-/H-Tile Avalon-ST for PCI Express IP Core supports the following features:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
  • ×1, ×2, ×4, ×8 and ×16 configurations with Gen1, Gen2, or Gen3 lane rates for Native Endpoints and Root Ports.
    Note: Root Port mode is not available when SR-IOV is enabled.
  • Avalon® -ST 256-bit interface to the Application Layer except for Gen3 x16 variants.
  • Avalon® -ST 512-bit interface at 250 MHz to the Application Layer for Gen3 x16 variants.
  • Instantiation as a stand-alone IP core from the Quartus® Prime Pro Edition IP Catalog or as part of a system design in Platform Designer.
  • Dynamic design example generation.
  • Configuration via Protocol (CvP) providing separate images for configuration of the periphery and core logic.
  • PHY interface for PCI Express (PIPE) or serial interface simulation using IEEE encrypted models.
  • Testbench bus functional model (BFM) supporting x1, x2, x4, and x8 configurations. The x16 configuration downtrains to x8 for Intel (internally created) testbench.
  • Support for a Gen3x16 simulation model that you can use in an Avery testbench. The Avery testbench is capable of simulating all 16 lanes. For more information, refer to AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Stratix® 10 Devices.
  • Native PHY Debug Master Endpoint (NPDME). For more information, refer to Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
  • Autonomous Hard IP mode, allowing the PCIe IP core to begin operation before the FPGA fabric is programmed. This mode is enabled by default. It cannot be disabled.
    Note: Unless Readiness Notifications mechanisms are used (see Section 6.23 of the PCIe Base Specification), the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device which fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • Dedicated 69.5 kilobyte (KB) receive buffer.
  • End-to-end cyclic redundancy check (ECRC).
  • Advanced Error Reporting (AER) for PFs.
    Note: In Stratix® 10 devices, Advanced Error Reporting is always enabled in the PCIe Hard IP for both the L- and H-Tile transceivers.
  • Base address register (BAR) checking logic.
  • The Intel L-/H-Tile Avalon-ST for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS)

New features in the Quartus® Prime Pro Edition 18.0 Software Release

  • SR-IOV support for H-Tile devices.
  • Separate Configuration Spaces for up to four PCIe Physical Functions (PFs) and a maximum of 2048 Virtual Functions (VFs) for the PFs in H-Tile devices.
  • Address Translation Services (ATS) and TLP Processing Hints (TPH) capabilities.
  • Control Shadow Interface to read the current settings for some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces.
  • Function Level Reset (FLR) for PFs and VFs.
  • Message Signaled Interrupts (MSI) for PFs.
  • MSI-X for PFs and VFs.
  • A PCIe* Link Inspector including the following features:
    • Read and write access to the Configuration Space registers.
    • LTSSM monitoring.
    • Read and write access to PCS and PMA registers.
  • Hardware support for dynamically-generated design examples.
  • A Linux software driver to test the dynamically-generated design examples.
Note: The purpose of the Stratix® 10 Avalon® -ST and Single Root I/O Virtualization (SR-IOV) Interfaces for Solutions User Guide is to explain how to use this IP. For a detailed understanding of the PCIe* protocol, please refer to the PCI Express* Base Specification.