L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

2. Quick Start Guide

Using Quartus® Prime software, you can generate a programmed I/O (PIO) design example for the Intel L-/H-Tile Avalon-ST for PCI Express IP core. The generated design example reflects the parameters that you specify. The PIO example transfers data from a host processor to a target device. It is appropriate for low-bandwidth applications. This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to the Stratix® 10-GX FPGA Development Board. To download to custom hardware, update the Quartus® Prime Settings File (.qsf) with the correct pin assignments .

Figure 12. Development Steps for the Design Example