L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

3.14. PLL Reconfiguration Interface

The PLL reconfiguration interface is an Avalon® -MM slave interface. Use this bus to dynamically modify the value of PLL registers that are read-only at run time.

This interface is available when you turn on Enable Transceiver dynamic reconfiguration on the Configuration, Debug and Extension Options tab using the parameter editor.

To ensure proper system operation, reset or repeat device enumeration of the PCIe* link after changing the value of read-only PLL registers.