L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

1.9. Channel Availability

PCIe Hard IP Channel Restrictions

Each L- or H-Tile transceiver tile contains one PCIe Hard IP block. The following table and figure show the possible PCIe Hard IP channel configurations, the number of unusable channels, and the number of channels available for other protocols. For example, a PCIe x4 variant uses 4 channels and 4 additional channels are unusable.

Table 6.  Unusable Channels
PCIe Hard IP Configuration Number of Unusable Channels Usable Channels
PCIe x1 7 16
PCIe x2 6 16
PCIe x4 4 16
PCIe x8 0 16
PCIe x16 0 8
Note: The PCIe Hard IP uses at least the bottom eight Embedded Multi-Die Interconnect Bridge (EMIB) channels, no matter how many PCIe lanes are enabled. Thus, these EMIB channels become unavailable for other protocols.
Figure 11. PCIe Hard IP Channel Configurations Per Transceiver Tile

The table below maps all transceiver channels to PCIe Hard IP channels in available tiles.

Table 7.  PCIe Hard IP channel mapping across all tiles
Tile Channel Sequence PCIe Hard IP Channel Index within I/O Bank Bottom Left Tile Bank Number Top Left Tile Bank Number Bottom Right Tile Bank Number Top Right Tile Bank Number
23 N/A 5 1F 1N 4F 4N
22 N/A 4 1F 1N 4F 4N
21 N/A 3 1F 1N 4F 4N
20 N/A 2 1F 1N 4F 4N
19 N/A 1 1F 1N 4F 4N
18 N/A 0 1F 1N 4F 4N
17 N/A 5 1E 1M 4E 4M
16 N/A 4 1E 1M 4E 4M
15 15 3 1E 1M 4E 4M
14 14 2 1E 1M 4E 4M
13 13 1 1E 1M 4E 4M
12 12 0 1E 1M 4E 4M
11 11 5 1D 1L 4D 4L
10 10 4 1D 1L 4D 4L
9 9 3 1D 1L 4D 4L
8 8 2 1D 1L 4D 4L
7 7 1 1D 1L 4D 4L
6 6 0 1D 1L 4D 4L
5 5 5 1C 1K 4C 4K
4 4 4 1C 1K 4C 4K
3 3 3 1C 1K 4C 4K
2 2 2 1C 1K 4C 4K
1 1 1 1C 1K 4C 4K
0 0 0 1C 1K 4C 4K

PCIe Soft IP Channel Usage

PCI Express soft IP PIPE-PHY cores available from third-party vendors are not subject to the channel usage restrictions described above. Refer to Intel FPGA PCI Express IP Support Center for more information about soft IP cores for PCI Express.