L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

4.6.2. Link Capabilities

Table 19.  Link Capabilities  




Link port number (Root Port only)


Sets the read-only value of the port number field in the Link Capabilities register. This parameter is for Root Ports only. It should not be changed.

Slot clock configuration


When you turn this option On, indicates that the Endpoint uses the same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector. This parameter sets the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register.