L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

8.1.1. Register Access Definitions

This document uses the following abbreviations when describing register access.
Table 55.  Register Access AbbreviationsSticky bits are not initialized or modified by hot reset or function-level reset.
Abbreviation Meaning
RW Read and write access
RO Read only
WO Write only
RW1C Read write 1 to clear
RW1CS Read write 1 to clear sticky
RWS Read write sticky