L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

5.4.2. Reset Requirements

The Intel L-/H-Tile Avalon-ST for PCI Express IP Core has two, asynchronous, active low reset inputs, npor and pin_perst. Both reset the Transaction, Data Link and Physical Layers.


The Application Layer drives the npor reset input to the PCIe IP core. If you choose to design an Application Layer does not drive npor, you must tie this output to 1'b1. The npor signal resets all registers and state machines to their initial values.


This is the PCI Express Fundamental Reset signal. Asserting this signal returns all registers and state machines to their initialization values. Each instance of the PCIe IP core has a dedicated pin_perst pin. You must connect the pin_perst of each hard IP instance to the corresponding nPERST pin of the device. These pins have the following location.
  • NPERSTL0 : Bottom Left PCIe IP core and Configuration via Protocol (CvP)
  • NPERSTL1: Middle Left PCIe PCIe IP core (When available)
  • NPERSTL2: Top Left PCIe IP core (When available)
  • NPERSTR0: Bottom Right PCIe IP core (When available)
  • NPERSTR1: Middle Right PCIe IP core (When available)
  • NPERSTR2: Top Right PCIe IP core (When available)
For maximum compatibility, always use the bottom PCIe IP core on the left side of the device first. This is the only location that supports CvP using the PCIe link.
Note: CvP is not available in the Quartus® Prime Pro – Stratix 10 Edition 17.1 Interim Release


When asserted, this signal indicates that the PCIe IP core is in reset. The reset_status signal is synchronous to coreclkout_hip. It is active high.


This signal has the same functionality as reset_status. It is provided for backwards compatibility with Arria® 10 devices. It is active high.