L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.1.5. Avalon-ST 512-Bit TX Interface

The Application Layer transfers data to the Transaction Layer of the PCI Express* IP core over the Avalon-ST TX interface. The 512-bit interface supports Gen3 x16 variants and uses a 250 MHz clock, simplifying timing closure.

The 512-bit interface supports two locations for the beginning of a TLP, bit[0] and bit[256]. The interface supports multiple TLPs per cycle only when an end-of-packet cycle occurs in the lower 256 bits.

Note: This interface is not strictly Avalon® -compliant because it supports two tx_st_sop signals and two tx_st_eop signals per cycle, and because there is a requirement of no ready and invalid cycle in the middle of a packet.
Table 34.  512‑Bit Avalon-ST TX Datapath






Application Layer data for transmission. The Application Layer must provide a properly formatted TLP on the TX interface. Valid when the tx_st_valid_o signal is asserted. The mapping of message TLPs is the same as the mapping of Transaction Layer TLPs with 4 dword headers. The number of data cycles must be correct for the length and address fields in the header. Issuing a packet with an incorrect number of data cycles results in the TX interface hanging and becoming unable to accept further requests.

For the TLP requester ID field, bits[31:16] in dword1 specify the following information:

  • Bits[19:16]: Specify the PF number.
  • Bits[31:20]: Specify the VF number. The VF number is valid when tx_st_vf_active is asserted. If the request is from VF[<m>,<n>], then bits[19:16] drive the PF number, <m>, and bits [31:20] drive the VF number, <n>. The tx_st_vf_active signal asserts in the same cycle as tx_st_sop and tx_st_valid.

For TLPs with an end-of-packet cycle in the lower 256 bits, the 512-bit interface supports a start-of-packet cycle in the upper 256 bits. If a TLP starts on bit 256, bits [319:304] specify the completer ID for Completion packets.



Indicates the first cycle of a TLP when asserted in conjunction with the corresponding bit of tx_st_valid_o. The following encodings are defined:

  • tx_st_sop_i[1]: When asserted indicates the start of a TLP in tx_st_data[511:256].
  • tx_st_sop_i[0]: When asserted indicates the start of a TLP in tx_st_data[255:0].


Indicates the end of a TLP when asserted in conjunction with the corresponding bit of tx_st_valid_o[1:0]. The following encodings are defined:

  • tx_st_eop_i[1]: When asserted indicates the end of a TLP in tx_st_data[511:256].
  • tx_st_eop_i[0]: When asserted indicates the end of a TLP in tx_st_data_i[255:0].



Indicates that the Transaction Layer is ready to accept data for transmission. The core deasserts this signal to apply backpressure to the data stream. The Application Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon-ST TX interface. The Application Layer can monitor the reset_status signal to determine when the IP core has come out of reset.

If tx_st_ready_o is asserted by the Transaction Layer on cycle <n> , then <n> + readyLatency is a ready cycle, during which the Application Layer may assert tx_st_valid_i and transfer data.

If the Transaction Layer deasserts tx_st_ready_o on cycle <n>, then the Application Layer must deassert tx_st_valid_i within a readyLatency number of cycles after cycle <n>.

The readyLatency is 3 coreclkout_hip cycles.



Clocks tx_st_data_i into the core on ready cycles. Between tx_st_sop_i and tx_st_eop_i, the tx_st_valid_i signal must not be deasserted in the middle of a TLP except in response to tx_st_ready deassertion. When tx_st_ready_o deasserts in the middle of a packet, this signal must deassert exactly 3 coreclkout_hip cycles later because the readyLatency is 3 cycles for this interface. When tx_st_ready_o reasserts, and tx_st_data is in mid-TLP, this signal must reassert on the next ready cycle. The figure entitled Avalon-ST TX Interface tx_st_ready Deasserts illustrates the timing of this signal. The behavior of this signal is the same for the 256- and 512-bit interfaces.

To facilitate timing closure, Intel recommends that you register both the tx_st_ready_o and tx_st_valid_i signals.

tx_st_err_i[1:0] Input When asserted, indicates an error on transmitted TLP. This signal is asserted with tx_st_eop_i and nullifies a packet. The following encodings are defined:
  • tx_st_err_i[1]: Specifies an error in tx_st_data[511:256].
  • tx_st_err_i[0]: Specifies an error in tx_st_data[255:0].
Note: You cannot nullify a packet with 8 DW or less of data.
tx_st_parity_i[63:0] Input Byte parity for tx_st_data_i. Bit 0 corresponds to tx_st_data_i[7:0], bit 1 corresponds to tx_st_data_i[15:8], and so on.
tx_st_vf_active[1:0] H-Tile Input

When asserted, the transmitting TLP is for a VF. When deasserted, the transmitting TLP is for a PF. Valid when tx_st_sop is asserted.

Valid when multiple functions are enabled.