L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents PCIe TLP Layout Using the 512-Bit Interface

The following figure illustrates TLP layout and provides three examples of TLP transmission with the correct encodings for the rx_st_sop[1:0], rx_st_eop[1:0], rx_st_valid_o[1:0] and rx_st_empty_o[5:0] signals.
Figure 43. Receiving PCIe TLPs Using 512-bit Avalon-ST Interface

Example 1: Two, Small TLPs

Example 1 illustrates the transmission of two, single-cycle TLPs. The TLP transmitted in the low-order bits has two empty dwords. The TLP transmitted in the high-order bits has no empty dwords.

Example 2: One, 6-DWord TLP

Example 2 shows the transmission of one, 6-dword PCI Express* . The low-order bits provide the header and the first four dwords of data. The high-order bits have the final two dwords of data. The rx_st_empty_o[5:3] vector indicates six empty dwords in the high-order bits. The rx_st_eop[1] bit indicates the end of the TLP in the high-order bits.

Example 3: One, 4-DWord TLP

Example 3 shows a single cycle packet in the low-order bits and no transmission in the high-order bits. The rx_st_valid_o[1] bit indicates that the high-order bits do not drive valid data.