L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.1.17. Hard IP Reconfiguration

The Hard IP Reconfiguration interface is an Avalon-MM slave interface with a 21‑bit address and an 8‑bit data bus. You can use this bus to dynamically modify the value of configuration registers that are read-only at run time.
Note that after a warm reset or cold reset, changes made to the configuration registers of the Hard IP via the Hard IP reconfiguration interface are lost as these registers revert back to their default values.

If the PCIe Link Inspector is enabled, accesses via the Hard IP Reconfiguration interface are not supported. The Link Inspector exclusively uses the Hard IP Reconfiguration interface, and there is no arbitration between the Link Inspector and the Hard IP Reconfiguration interface that is exported to the top level of the IP.

Table 46.  Hard IP Reconfiguration Signals






Reconfiguration clock. The frequency range for this clock is 100–125 MHz.



Active-low Avalon-MM reset for this interface.



The 21‑bit reconfiguration address.

When the Hard IP reconfiguration feature is enabled, the hip_reconfig_address[20:0] bits are programmable.

Some bits have the same functions in both H-Tile and L-Tile:

  • hip_reconfig_address[11:0]: Provide full byte access to the 4 Kbytes PCIe* configuration space.
    Note: For the address map of the PCIe* configuration space, refer to the Configuration Space Registers section in the Registers chapter.
  • hip_reconfig_address[20]: Should be set to 1'b1 to indicate PCIe* space access.

Some bits have different functions in H-Tile versus L-Tile:

For H-Tile:

  • hip_reconfig_address[13:12]: Provide the PF number. Since the H-Tile can support up to four PFs, two bits are needed to encode the PF number.
  • hip_reconfig_address[19:14]: Reserved. They must be driven to 0.

For L-Tile:

  • hip_reconfig_address[12]: Provides the PF number. Since the L-Tile only supports up to two PFs, one bit is sufficient to encode the PF number.
  • hip_reconfig_address[19:13]: Reserved. They must be driven to 0.


Read signal. This interface is not pipelined. You must wait for the return of the hip_reconfig_readdata[7:0] from the current read before starting another read operation.



8‑bit read data. hip_reconfig_readdata[7:0] is valid on the third cycle after the assertion of hip_reconfig_read.

hip_reconfig_readdatavalid Output When asserted, the data on hip_reconfig_readdata[7:0] is valid.


Write signal.



8‑bit write model.

hip_reconfig_waitrequest Output When asserted, indicates that the IP core is not ready to respond to a request.