L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.4.2. RX TLP Ordering

TLPs ordering on the Avalon® -ST RX interface is determined by the available credits for each TLP type and the PCIe ordering rules. Refer to Table 2-34 Ordering Rules Summary in the PCI Express Base Specification Revision 3.0 for a summary of the ordering rules.

The IP core implements relaxed ordering as described in the PCI Express Base Specification Revision 3.0. It does not perform ID-Based Ordering (IDO). The Application Layer can implement IDO reordering. It is possible for two different TLP types pending in the RX buffer to have equal priority. When this situation occurs, the IP core uses a fairness-based arbitration scheme to determine which TLP to forward to the Application Layer.