L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

7.1.1. MSI and Legacy Interrupts

The IP core generates single dword Memory Write TLPs to signal MSI interrupts on the PCI Express link. The Application Layer Interrupt Handler Module app_msi_req output port controls MSI interrupt generation. When asserted, it causes an MSI posted Memory Write TLP to be generated. The IP core constructs the TLP using information from the following sources:
  • The MSI Capability registers
  • The traffic class (app_msi_tc)
  • The message data specified by app_msi_num
To enable MSI interrupts, the Application Layer must first set the MSI enable bit. Then, it must disable legacy interrupts by setting the Interrupt Disable, bit 10 of the Command register.

Whenever the IP core gets an MSI request from the Interrupt Handler Module in the application layer (via the app_msi_req signal), it will generate an MSI TLP no matter the state of the MSI Enable or Bus Master Enable bits. The application logic must gate the MSI TLP based on the state of those bits.

Figure 53. Interrupt Handler Module in the Application Layer

The following figure illustrates a possible implementation of the Interrupt Handler Module with a per vector enable bit. Alternatively, the Application Layer could implement a global interrupt enable instead of this per vector MSI.

Figure 54. Example Implementation of the Interrupt Handler Block

There are 32 possible MSI messages. The number of messages requested by a particular component does not necessarily correspond to the number of messages allocated. For example, in the following figure, the Endpoint requests eight MSIs but is only allocated two. In this case, you must design the Application Layer to use only two allocated messages.

Figure 55. MSI Request Example

The following table describes three example implementations. The first example allocates all 32 MSI messages. The second and third examples only allocate 4 interrupts.

Table 52.  MSI Messages Requested, Allocated, and Mapped






System Error




Hot Plug and Power Management Event




Application Layer




MSI interrupts generated for Hot Plug, Power Management Events, and System Errors always use Traffic Class 0. MSI interrupts generated by the Application Layer can use any Traffic Class. For example, a DMA that generates an MSI at the end of a transmission can use the same traffic control as was used to transfer data.

The following figure illustrates the interactions among MSI interrupt signals for the Root Port. The minimum latency possible between app_msi_req and app_msi_ack is one clock cycle. In this timing diagram app_msi_req can extend beyond app_msi_ack before deasserting. In other words, the earliest that app_msi_req can deassert is on the rising edge of clock cycle 5 (one cycle after app_msi_ack is asserted) as shown, but it can deassert in later clock cycles as well.

Figure 56. MSI Interrupt Signals Timing
By default, the Intel L-/H-tile Avalon Streaming IP for PCI Express provides support for MSI messages with 32-bit addresses. The 64-bit address support on MSI messages can be enabled with the pfX_pci_msi_64_bit_addr_cap parameter on the top-level entity. Use the following steps to enable the feature:
  1. Open the top-level file of the Intel L-/H-tile Avalon Streaming IP for PCI Express (<ip_name>/synth/<ip_name>.v).
  2. Locate the <ip_name>_altera_pcie_s10_hip_ast_<ip_version>_<auto_generated_postfix> and set the pfX_pci_msi_64_bit_addr_cap parameter to True for each physical function that requires the 64-bit address MSI support.
  3. Save the changes and recompile your project without regenerating the files.