L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

4.2. Multifunction and SR-IOV System Settings

Table 13.  Multifunction and SR-IOV System Settings




Total Physical Functions (PFs) :

1 - 4

Supports 1 - 4 PFs (in H-Tile devices).

Enable SR-IOV Support On/Off

When On, the variant supports multiple VFs. When Off, supports PFs only. SR-IOV is only available in H-Tile devices.

Total Virtual Functions Assigned to Physical Functions:

1 - 2048

Total number of VFs assigned to a PF. The sum of VFs assigned to PF0, PF1, PF2, and PF3 cannot exceed the 2048 VFs total.

System Supported Page Size: 4 KB-4 MB

Specifies the page sizes supported. Sets the Supported Page Sizes register of the SR-IOV Capability structure.

Intel recommends that you accept the default value.

Note: Throughout this document, the terminology "Physical Function" and "PF" refer to what is defined as "Physical Function" in the PCI Express SR-IOV Specification when SR-IOV is enabled, and to what is defined simply as "Function" in the PCI Express Base Specification when SR-IOV is not enabled.
Note: In a multifunction application, if two or more functions initiate Memory Read requests with identical tag values, the Stratix® 10 Avalon® -ST Hard IP for PCIe IP Core only stores the latest Completion that it receives. Therefore, even though Completions for Memory Reads from different functions have different requester ID fields, if they share the same tag, only the last Completion with that tag value to arrive is preserved. To avoid lost Completion packets, the user application must not use the same tag for Memory Read transactions across multiple functions.