L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.3.1. Endpoint D3 Entry

This topic outlines the D3 power-down procedure.

All transmission on the Avalon® -ST TX and RX interfaces must have completed before IP core can begin the L1 request (Enter_L1 DLLP). In addition, the RX Buffer must be empty and the Application Layer app_xfer_pending output must be deasserted.

  1. Software writes the Power Management Control register to put the IP core to the D3hot state.
  2. The Endpoint stops transmitting requests when it has been taken out of D0.
  3. The link transitions to L1.
  4. Software sends the PME_Turn_Off Message to the Endpoint to initiate power down. The Root Port transitions the link back to L0, and Endpoint receives the Message on the Avalon® -ST RX interface.
  5. The Endpoint transmits a PME_TO_Ack Message to acknowledge the Turn Off request. Since this message is handled by the IP, the Application Layer does not need to handle it.
  6. When ready for power removal, (D3cold), the End Point asserts apps_ready_entr_l23. The core sends the PM_Enter_L23 DLLP and initiates the Link transition to L3.