L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.1.7. Interpreting the TX Credit Interface

The Stratix® 10 PCIe TX credit interface reports the number of Flow Control credits available.

The following equation defines the available buffer space of the link partner:

RX_buffer_space = (credit_limit - credits_consumed)+ released_credits


credits_consumed = credits_consumedapplication + credits_consumedPCIe_IP_core 

The hard IP core consumes a small number of posted credits for the following reasons:

  • To send completion TLPs for Configuration Requests targeting internal registers
  • To transmit posted TLPs for error and interrupt Messages

The hard IP core does not report the internally consumed credits to the Application. Without knowing the hard IP core's internal usage, the Application cannot maintain a completely accurate count of Posted or Completion credits.

The hard IP core does not consume non-posted credits. Consequently, it is possible to maintain an accurate count of the available non-posted credits. Refer to the TX Credit Adjustment Sample Code for code that calculates the number of non-posted credits available to the Application. This RTL recovers the updated Flow Control credits from the remote link. It drives the value of the link partner's RX_buffer_space for non-posted header and data credits on tx_nph_cdts and tx_npd_cdts, respectively.

Figure 48. Flow Control Credit Update LoopThe following figure provides an overview of the steps to determine credits available and release credits after the TLP is removed from the link partner's RX buffer.
Note: To avoid a potential deadlock or performance degradation, the Application should check available credits before sending a TLP to the Intel L-/H-Tile Avalon-ST for PCI Express IP Core. If the Application cannot send Non-Posted packets, it must be allowed to send other types of packets.