L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

9.1. Endpoint Testbench

You can create an Endpoint design for inclusion in the testbench using design flows described in the Quick Start Guide. This testbench uses the parameters that you specify in the Quick Start Guide.

This testbench simulates up to an ×8 PCI Express link using either the PIPE interface of the Endpoint or the serial PCI Express interface. The testbench design does not allow more than one PCI Express link to be simulated at a time. The following figure presents a high level view of the design example.

Figure 70. Design Example for Endpoint Designs

The top-level of the testbench instantiates the following main modules:

  • altpcietb_bfm_rp_<gen>_x8.sv —This is the Root Port PCIe* BFM. This is the module that you modify to vary the transactions sent to the example Endpoint design or your own design.
    //Directory path
    Note: If you modify the RP BFM, you must also make the appropriate corresponding changes the APPs module.
  • pcie_example_design_DUT.ip: This is the Endpoint design with the parameters that you specify.
    //Directory path
  • pcie_example_design_APPS.ip: This module is a target and initiator of transactions.
    //Directory path
  • altpcietb_bfm_cfpb.v: This module supports Configuration Space Bypass mode. It drives TLPs to the custom Configuration Space.
    //Directory path

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.
Note: Before running the testbench, you should set the serial_sim_hwtcl parameter in <testbench_dir>/pcie_<dev>_hip_avst_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/DUT_pcie_tb_ip/altera_pcie_<dev>_tbed_<ver>/sim/altpcie__tbed_hwtcl.v. Set to 1 for serial simulation and 0 for PIPE simulation.