L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6. Block Descriptions

The Intel L-/H-Tile Avalon-ST for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification. The protocol stack includes the following layers:

  • Transaction Layer—The Transaction Layer contains the Configuration Space, which manages communication with the Application Layer, the RX and TX channels, the RX buffer, and flow control credits.
  • Data Link Layer—The Data Link Layer, located between the Physical Layer and the Transaction Layer, manages packet transmission and maintains data integrity at the link level. Specifically, the Data Link Layer performs the following tasks:
    • Manages transmission and reception of Data Link Layer Packets (DLLPs)
    • Generates all transmission link cyclical redundancy code (LCRC) values and checks all LCRCs during reception
    • Manages the retry buffer and retry mechanism according to received ACK/NAK Data Link Layer packets
    • Initializes the flow control mechanism for DLLPs and routes flow control credits to and from the Transaction Layer
  • Physical Layer—The Physical Layer initializes the speed, lane numbering, and lane width of the PCI Express link according to packets received from the link and directives received from higher layers. The following figure provides a high‑level block diagram.
Figure 32.  Intel L-/H-Tile Avalon-ST for PCI Express

Each channel of the Physical Layer is paired with an Embedded Multi-die Interconnect Bridge (EMIB) module. The FPGA fabric interfaces to the PCI Express IP core through the EMIB.