L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.5. RX Buffer

The Receive Buffer stores TLPs received from the PCI Express link. The RX Buffer stores the entire TLP before it forwards it to the Application Layer.
Storing the entire TLP allows the IP to accomplish two things:
  • The IP core can rate match the PCIe link to the Application Layer.
  • The IP core can store TLPs until error checking is complete.
The 64 KB RX buffer has separate buffer space for Posted, Non-Posted and Completion TLPS. Headers and data also have separate allocations. The RX Buffer enables full bandwidth RX traffic for all three types of TLPs simultaneously.
Table 51.  Flow Control Credit AllocationThe buffer allocation is fixed.
RX Buffer Segment Number of Credits Buffer Size

Posted headers: 127 credits

Posted data: 750 credits

~14 KB
Non-posted Non-posted headers credits: 115 credits

Non-posted data credits: 230 credits

~5.5 KB
Completions Completion headers: 770 credits

Completion data: 2500 credits

~50 KB

The RX buffer operates only in the Store and Forward Queue Mode. Bypass and Cut-through modes are not supported.

Flow control credit checking for the posted and non-posted buffer segments prevents RX buffer overflow. The PCI Express Base Specification Revision 3.0 requires the IP core to advertise infinite Completion credits. The Application Layer must manage the Read Requests so as not to overflow the Completion buffer segment.