L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents Avalon-ST TX Three- and Four-Dword TLPs

These timing diagrams illustrate the layout of headers and data for the Avalon-ST TX interface.
Figure 44. Avalon-ST TX Interface Cycle Definition for Three-Dword Header TLPs
Figure 45. Avalon-ST TX Interface Cycle Definition for Four-Dword Header TLPs