L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

7.1. Interrupts for Endpoints

The Intel L-/H-Tile Avalon-ST for PCI Express IP provides support for PCI Express MSI, MSI-X, and legacy interrupts when configured in Endpoint mode. The MSI and legacy interrupts are mutually exclusive. After power up, the Hard IP block starts in legacy interrupt mode. Then, software decides whether to switch to MSI or MSI-X mode. To switch to MSI mode, software programs the msi_enable bit of the MSI Message Control Register to 1, (bit[16] of 0x050). You enable MSI-X mode, by turning on Implement MSI-X under the PCI Express/PCI Capabilities tab using the parameter editor. If you turn on the Implement MSI-X option, you should implement the MSI-X table structures at the memory space pointed to by the BARs.


Refer to section 6.1 of PCI Express Base Specification for a general description of PCI Express interrupt support for Endpoints.