L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents Assertion and Deassertion of Avalon-ST TX Interface tx_st_valid

You must not deassert tx_st_valid between the tx_st_sop and tx_st_eop on a ready cycle. For the definition of a ready cycle, refer to Avalon Interface Specifications.

Note: This is an additional requirement for the PCIe Hard IP that is not compliant to the Avalon® -ST standard.

The following timing diagram shows an example where tx_st_ready deasserts in the middle of a packet and then reasserts, causing tx_st_valid to also deassert and then reassert.

Figure 47. Proper Assertion and Deassertion of tx_st_valid