L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.1.11. Resets

An embedded hard reset controller (HRC) generates the reset for PCIe core logic, PMA, PCS, and Application. To support the 100 ms PCIe wake-up time, the embedded reset controller connects to the SDM. This connection allows the FPGA periphery to configure and begin operation before the FPGA fabric is programmed.

The reset logic requires a free running clock that is stable and available to the IP core at configuration time.

Figure 51.  Intel L-/H-Tile Avalon-ST for PCI Express Reset Controller The signals shown in the Hard IP for PCIe Reset Controller are implemented in hard logic and not available for probing.
Table 40.  Resets




currentspeed[1:0] Output

Indicates the current speed of the PCIe module. The following

encodings are defined:
  • 2'b00: Undefined
  • 2'b01: Gen1
  • 2'b10: Gen2
  • 2'b11: Gen3


The Application Layer drives this active low reset signal. npor resets the entire IP core, PCS, PMA, and PLLs. npor should be held for a minimum of 20 ns. Gen3 x16 variants, should hold npor for at least 10 cycles. This signal is edge, not level sensitive; consequently, a low value on this signal does not hold custom logic in reset. This signal cannot be disabled.


Active low reset from the PCIe reset pin of the device. Resets the datapath and control registers.
ninit_done Input This is an active-low asynchronous input. A "1" on this signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Avalon® streaming IP for PCIe. For more details on how to use this input, refer to Including the Reset Release Intel® FPGA IP in Your Design.


Output This reset signal has the same effect as reset_status. This signal is provided for backwards compatibility with Arria® 10 devices.


Input When asserted, indicates that the Application Layer is ready. The IP core can releases reset after this signal is asserted.


Output Active high reset status. When high, indicates that the IP core is not ready for usermode. reset_status is deasserted only when npor is deasserted and the IP core is not in reset. Use reset_status to drive the reset of your application. Synchronous to coreclkout_hip.



clr_st has the same functionality as reset_status. It is provided for backwards compatibility with previous device families.



When asserted, indicates that the PLL that generates coreclkout_hip is locked. In pipe simulation mode this signal is always asserted.