L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

3.2. Avalon-ST TX Interface

The Application transmits TLPs to the Transaction Layer of the IP core on this interface. The Transaction Layer must assert tx_st_ready before transmission begins. Transmission of a packet must be uninterrupted when tx_st_ready is asserted. The readyLatency of this interface is three coreclkout_hip cycles. For more detailed information about the Avalon-ST interface, refer to Avalon-ST TX Interface. The packet layout is shown in detail in the Block Description chapter.

Note: In Stratix® 10 devices, the Avalon-ST TX interface does not support Root Port mode Configuration requests in which Configuration Type 0 TLPs are sent to the PCIe Hard IP to read/write the local Configuration Space registers. Instead of using the Avalon-ST TX interface, you can use the Hard IP Reconfiguration interface to access the PCIe Hard IP's local Configuration Space.