L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

6.3.3. Exit from D3 hot

The Power Management Capability register must enable D3Hot PME_Support. In addition, software must set the PME_en bit in the Power Management Control and Status register.