L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 9/12/2024
Public
Document Table of Contents

8.1.5. General Purpose Control and Status Register

This register provides up to eight I/O pins for Application Layer control and status requirements. This feature supports Partial Reconfiguration of the FPGA fabric. Partial Reconfiguration only requires one input and one output pin. The other seven I/Os make this interface extensible.
Table 61.  General Purpose Control and Status Register - 0xBB0

Bits

Register Description

Default Value

Access

[31:16] Reserved. N/A RO

[15:8]

General Purpose Status. The Application Layer can read status bits. 0

RO

[7:0]

General Purpose Control. The Application Layer can write control bits. 0

RW