L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

5.4.1. Clock Requirements

The Intel L-/H-Tile Avalon-ST for PCI Express IP Core has a single 100 MHz input clock and a single output clock. An additional clock is available for PIPE simulations only.


Each instance of the PCIe IP core has a dedicated refclk input signal. This input reference clock can be sourced from any reference clock in the transceiver tile. Refer to the Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines for additional information on termination and valid locations.


This output clock is a fixed frequency clock that drives the Application Layer. The output clock frequency is derived from the maximum link width and maximum link rate of the PCIe IP core.
Table 29.  Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and Application Layer Interface Widths
Maximum Link Rate Maximum Link Width Avalon-ST Interface Width

coreclkout_hip Frequency

Gen1 x1, x2, x4, x8, x16 256 125 MHz
Gen2 x1, x2, x4, x8 256 125 MHz
Gen2 x16 256 250 MHz
Gen3 x1, x2, x4 256 125 MHz
Gen3 x8 256 250 MHz
Gen3 x16 512 250 MHz


This input clock is for PIPE simulation only. Derived from the refclk input, sim_pipe_pclk_in is the PIPE interface clock for PIPE mode simulation.