L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide
ID
683111
Date
9/12/2024
Public
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Interrupts
8. Registers
9. Testbench and Design Example
10. Document Revision History
A. PCI Express Core Architecture
B. TX Credit Adjustment Sample Code
C. Root Port Enumeration
D. Troubleshooting and Observing the Link Status
1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Recommended Fabric Speed Grades
1.6. Performance and Resource Utilization
1.7. Transceiver Tiles
1.8. PCI Express IP Core Package Layout
1.9. Channel Availability
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
3.1. Avalon-ST RX Interface
3.2. Avalon-ST TX Interface
3.3. TX Credit Interface
3.4. TX and RX Serial Data
3.5. Clocks
3.6. Function-Level Reset (FLR) Interface
3.7. Control Shadow Interface for SR-IOV
3.8. Configuration Extension Bus Interface
3.9. Hard IP Reconfiguration Interface
3.10. Interrupt Interfaces
3.11. Power Management Interface
3.12. Reset
3.13. Transaction Layer Configuration Interface
3.14. PLL Reconfiguration Interface
3.15. PIPE Interface (Simulation Only)
4.1. Stratix 10 Avalon-ST Settings
4.2. Multifunction and SR-IOV System Settings
4.3. Base Address Registers
4.4. Device Identification Registers
4.5. TPH/ATS Capabilities
4.6. PCI Express and PCI Capabilities Parameters
4.7. Configuration, Debug and Extension Options
4.8. PHY Characteristics
4.9. Example Designs
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces
6.1.2. Avalon-ST 256-Bit RX Interface
6.1.3. Avalon-ST 512-Bit RX Interface
6.1.4. Avalon-ST 256-Bit TX Interface
6.1.5. Avalon-ST 512-Bit TX Interface
6.1.6. TX Credit Interface
6.1.7. Interpreting the TX Credit Interface
6.1.8. Clocks
6.1.9. Update Flow Control Timer and Credit Release
6.1.10. Function-Level Reset (FLR) Interface
6.1.11. Resets
6.1.12. Interrupts
6.1.13. Control Shadow Interface for SR-IOV
6.1.14. Transaction Layer Configuration Space Interface
6.1.15. Configuration Extension Bus Interface
6.1.16. Hard IP Status Interface
6.1.17. Hard IP Reconfiguration
6.1.18. Power Management Interface
6.1.19. Serial Data Interface
6.1.20. PIPE Interface
6.1.21. Test Interface
6.1.22. PLL IP Reconfiguration
6.1.23. Message Handling
8.1.1. Register Access Definitions
8.1.2. PCI Configuration Header Registers
8.1.3. PCI Express Capability Structures
8.1.4. Intel Defined VSEC Capability Header
8.1.5. General Purpose Control and Status Register
8.1.6. Uncorrectable Internal Error Status Register
8.1.7. Uncorrectable Internal Error Mask Register
8.1.8. Correctable Internal Error Status Register
8.1.9. Correctable Internal Error Mask Register
8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map
8.1.10.1. ARI Enhanced Capability Header
8.1.10.2. SR-IOV Enhanced Capability Registers
8.1.10.3. Initial VFs and Total VFs Registers
8.1.10.4. VF Device ID Register
8.1.10.5. Page Size Registers
8.1.10.6. VF Base Address Registers (BARs) 0-5
8.1.10.7. Secondary PCI Express Extended Capability Header
8.1.10.8. Lane Status Registers
8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
8.1.10.10. TPH Requester Capability Register
8.1.10.11. TPH Requester Control Register
8.1.10.12. Address Translation Services ATS Enhanced Capability Header
8.1.10.13. ATS Capability Register and ATS Control Register
9.4.1. ebfm_barwr Procedure
9.4.2. ebfm_barwr_imm Procedure
9.4.3. ebfm_barrd_wait Procedure
9.4.4. ebfm_barrd_nowt Procedure
9.4.5. ebfm_cfgwr_imm_wait Procedure
9.4.6. ebfm_cfgwr_imm_nowt Procedure
9.4.7. ebfm_cfgrd_wait Procedure
9.4.8. ebfm_cfgrd_nowt Procedure
9.4.9. BFM Configuration Procedures
9.4.10. BFM Shared Memory Access Procedures
9.4.11. BFM Log and Message Procedures
9.4.12. Verilog HDL Formatting Functions
5.3. IP Core Generation Output ( Quartus® Prime Pro Edition)
The Quartus® Prime software generates the following output file structure for individual IP cores that are not part of a Platform Designer system.
File Name | Description |
---|---|
<your_ip>.ip | Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file. |
<your_ip>.cmp | The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files. |
<your_ip>_generation.rpt | IP or Platform Designer generation log file. Displays a summary of the messages during IP generation. |
<your_ip>.qgsimc (Platform Designer systems only) | Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qgsynth (Platform Designer systems only) | Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.csv | Contains information about the upgrade status of the IP component. |
<your_ip>.bsf | A symbol representation of the IP variation for use in Block Diagram Files (.bdf). |
<your_ip>.spd | Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize. |
<your_ip>.ppf | The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner. |
<your_ip>_bb.v | Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox. |
<your_ip>_inst.v or _inst.vhd | HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation. |
<your_ip>.regmap | If the IP contains register information, the Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of host and agent interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console. |
<your_ip>.svd | Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system. During synthesis, the Quartus® Prime software stores the .svd files for agent interface visible to the System Console hosts in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system agents, Platform Designer accesses the registers by name. |
<your_ip>.v <your_ip>.vhd |
HDL files that instantiate each submodule or child IP core for synthesis or simulation. |
mentor/ | Contains a msim_setup.tcl script to set up and run a simulation with a supported Siemens EDA simulator, such as the QuestaSim simulator. |
aldec/ | Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation. |
/synopsys/vcs /synopsys/vcsmx |
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS* MX simulation. |
/xcelium | Contains an Xcelium* Parallel simulator shell script xcelium_setup.sh and other setup files to set up and run a simulation. |
/submodules | Contains HDL files for the IP core submodule. |
<IP submodule>/ | Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates. |
Figure 21. Individual IP Core Generation Output ( Quartus® Prime Pro Edition)