L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents MSI and Legacy Interrupts

Message Signaled Interrupts (MSI) interrupts are signaled on the PCI Express link using a single dword Memory Write TLP.
Table 41.  MSI and Legacy Interrupts






Application Layer MSI request. Assertion causes an MSI posted write TLP to be generated based on the MSI configuration register values and the app_msi_tc and app_msi_num input ports. The Application Layer can deassert this MSI request signal any time after app_msi_ack has been asserted to acknowledge the request.



The IP core acknowledges theapp_msi_req request. Asserts for 1 cycle to acknowledge the Application Layer's request for an MSI interrupt. The Application Layer can deassert the app_msi_req request as soon as it receives this signal.



Application Layer MSI traffic class. This signal indicates the traffic class used to send the MSI (unlike INTX interrupts, any traffic class can be used to send MSIs).



MSI number of the Application Layer. The application uses the app_msi_num bus to indicate the offset between the base message data and the MSI to send. When multiple message mode is enabled, it sets the lower five bits of the MSI Data register. Only bits that the MSI Message Control register enables apply.

app_int_sts[3:0] H-Tile


Controls legacy interrupts. Assertion of app_int_sts causes an Assert_INTx message TLP to be generated and sent upstream. Deassertion of app_int_sts causes a Deassert_INTx message TLP to be generated and sent upstream.

When you enable multiple PFs, bit 0 is for PF0, bit 1 is for PF1, and so on.

app_msi_func_num[1:0] H-Tile

Input Specifies the function number requesting an MSI transmission.

app_err_func_num[1:0] H-Tile

Input Specifies the function number that is asserting the app_err_valid signal.