L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Document Table of Contents

5.5.2. TX PLL

For Gen1 or Gen2, the PCIe IP core uses the fractional PLL ( fPLL) for the TX PLL. For Gen3, the PCIe Hard IP core uses the fPLL when operating at the Gen1 or Gen2 data rate. It uses the advanced transmit (ATX) PLL when operating at the Gen3 data rate.
Note: The ATX PLL is sometimes called the LC PLL, where LC refers to inductor/capacitor.