- 6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express
|Intel® Quartus® Prime Design Suite 22.4|
Configuration via Protocol (CvP) is a configuration scheme supported in Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Cyclone® 10 GX device families. The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the Intel® FPGA fabric through the PCI Express* ( PCIe* ) link, and is available for Endpoint variants only. This document describes the CvP configuration scheme for Intel® Stratix® 10 device family. The CvP configuration scheme targets core fabric configuration through PCIe* link, which means it only supports FPGA Configuration First Mode even you use Intel® Stratix® 10 SoC devices.
Benefits of Using CvP
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