Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 11/10/2023
Document Table of Contents

1.2. CvP System

A CvP system typically consists of an FPGA, a PCIe* host, and a configuration device.
Figure 1. CvP Block Diagram
  1. The FPGA connects to the configuration device using the Active Serial x4 (fast mode) configuration scheme.
  2. CvP and other applications use the PCIe* Hard IP block (bottom left).
    Note: For information about the location of the PCIe* Hard IP blocks, refer to Table: PCIe Hard IP channel mapping across all tiles in Channel Availability section of the Intel Stratix 10 H-Tile and L-Tile Avalon Memory Mapped Hard IP for PCI Express* User Guide.
    • Many Intel® Stratix® 10 FPGAs include more than one Hard IP block for PCI Express* . The CvP configuration scheme can only utilize the bottom left PCIe* Hard IP block on each device. You must configure this as an Endpoint.

  3. PCIe* Hard IP tile (non-bottom left tile) can only be used for PCIe* applications and cannot be used for CvP.
Note: To avoid configuration failure, you must provide a free running and stable reference clock source to PCIe* IP core before you start the configuration.
Note: For PCIe design including Configuration via Protocol (CvP), Intel recommends you to use Micron QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Intel recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enter link training state before PERST# deasserted.