Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 11/10/2023
Document Table of Contents Programming CvP Images

In Active Serial configuration mode, you must program the periphery image (.periph.jic) into your AS configuration device and then download the core image (.core.rbf) using the PCIe Link. You can use Active Serial x4 (Fast mode) to load .periph.jic into your selected CvP initialization enabled Intel® Stratix® 10 device.

After loading the periphery image, the Intel® Stratix® 10 is triggered to reconfigure from AS to load it. The link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities. Follow these steps to program and test the CvP functionality:

  1. Plug the Intel® Stratix® 10 FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. Intel recommends you use the ATX power supply included with the development kit.
  2. Open the Intel® Quartus® Prime Tools menu and select Programmer.
  3. Click Auto Detect to verify that the Intel® FPGA Download Cable recognizes the Intel® Stratix® 10 FPGA.
  4. Follow these steps to program the periphery image:
    1. Select Stratix 10 device, and then right click None under File column and select Change File.
    2. Navigate to .periph.jic file and click Open.
    3. Under Program/Configure column, select the respective devices. For example, 1SG280LU3S1 and EPCQL1024.
    4. Click Start to program the periphery image into EPCQL1024 flash.
    Figure 14. Illustrating the Specified Options to the Program Periphery Image
  5. After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel® Stratix® 10 FPGA Development Kit.
  6. You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
  7. Follow these steps to program the core image via PCIe link:
    1. Copy the .core.rbf file into /lib/firmware
    2. In the /lib/firmware directory, run the following command to use the FPGA manager to configure the core image.
      • Run: su to get root access.
      • Run:
        echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name
  8. You can see your core image running on the Intel® Stratix® 10 FPGA Development Kit. Alternatively, print out the kernel message using the dmesg to ensure the CvP is completed successfully.