- 6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express
2.4. Pin Description
|Pin Name||Pin Type||Pin Description||Pin Connection|
|CvP_CONFDONE||Output||The CvP_CONFDONE pin is driven low during configuration. When configuration via PCIe* is complete, this signal is actively driven high.
During FPGA configuration in CvP initialization and update mode, you may observe this pin after the CONF_DONE pin goes high to determine if the FPGA is successfully configured.
|If this pin is set as dedicated output, the VCCIO_SDM power supply must meet the input voltage specification of the receiving side.
You can assign SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15 or SDM_IO16 as CvP_CONFDONE in Intel® Quartus® Prime Pro Edition software
|INIT_DONE||Output||The INIT_DONE pin goes high indicating the device has entered user mode upon completion of configuration.|| Intel recommends using SDM_IO0 pin for implementing the INIT_DONE function, provided that this function is enabled in the Intel® Quartus® Prime Pro Edition software. This pin has a weak pull-down for the correct function during power up.
The INIT_DONE function can also be implemented using other unused SDM I/O pins (with a weak pull-down).
For normal configuration mode, the CONF_DONE pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, CONF_DONE is driven high.
In CvP initialization mode, CONF_DONE goes high after the periphery is configured.
Intel recommends using SDM_IO16 pin implementing the CONF_DONE function, provided that this function is enabled in the Intel® Quartus® Prime Pro Edition software.
|nPERST[L,R][0:2]||Input||The nPERST pin is only available when you use PCI Express* hard IP.
When the PCIe* hard IP on a side (left or right) is enabled, then nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe* nPERST signal to ensure that both ends of the link start link-training at the same time.
The nPERST pins on a side are available as GPIOs only when the PCIe* hard IP on that side is not enabled.
When this pin is low, the transceivers are in reset. When this pin is high, the transceivers are out of reset.
When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin
|Connect this pin as defined in the Intel® Quartus® Prime Pro Edition software. For more details, refer to Intel® Stratix® 10 Avalon® -MM/ST Interface for PCIe* Solutions User Guide.
This pin is powered by the VCCIO3V supply.
When you connect a 3.0-V supply to VCCIO3V, you must use a diode to clamp the 3.3V LVTTL PCIe* input signal to the VCCIO3V power of the device.
When VCCIO3V is connected to any voltage other than 3.0V, you must use a level translator to shift down the voltage from 3.3V LVTTL to the corresponding voltage level powering the VCCIO3V pin.
Only one nPERST pin is used per PCIe* hard IP. The Intel® Stratix® 10 device components may have all six pins listed even when the specific component might only have 1 or 2 PCIe* hard IPs:
Note: For maximum compatibility, always use the bottom left PCIe* Hard IP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe* link.
Did you find the information on this page useful?